1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, more particularly, to an integrated circuit of a multiple die package structure including a plurality of semiconductor devices having on-die termination (ODT) circuits.
2. Description of the Related Art
An electronic system includes a controller and a semiconductor device that communicate with each other through at least one system bus. The system bus is used as a transmission line. Thus, a system bus is generally designed based on a signal reflection related to a device coupled to the transmission line. The transmission line is terminated using a resistor coupled between the transmission line and a power node.
In an external system such as a computer, a termination may be provided by an external resistor arranged on a motherboard of the computer. The external resistor having an impedance matched with an impedance of a transmission line is selected and terminates the transmission line such as a signal coupling line coupled to a plurality of integrated circuits. When the external resistor is matched with the impedance of the transmission line, a signal reflection is nearly nonexistent. But, the external resistor arranged on a system motherboard occupies a large space of the system board.
An on-chip termination (OCT) or on-die termination (ODT) as an activation termination instead of an external resistor may be used in an integrated circuit of a system. The active termination represents that a termination resistor is inserted into an internal part of a semiconductor device, and a controller and a termination resistance value is varied by turning on/off the termination resistor. Here, a value of the termination resistor may be controlled by a controller using an internal setting method of a semiconductor device such as a mode register set (MRS).
Moreover, it may be requested to turn off the active termination to minimize a current consumption according to an operation of a semiconductor device. For this operation, in a conventional art, termination setting values may be converted to ‘0’ in the MRS, or an operation signal of the active termination, which is inputted to the semiconductor device, may be disabled. Here, the latter is preferable compared to the former.
That is, when the operation signal of the active termination is enabled, the active termination operation is included in an operation of the semiconductor device. But, when the operation signal of the active termination is disabled or termination setting values of the MRS are converted to ‘0’ while the operation signal of the active termination is enabled, the active termination operation is not included in the operation of the semiconductor device.
Meanwhile, a semiconductor device, which operates at a high speed, reduces a switching noise of an input/output signal using a power supply voltage termination (VDDQ termination). According to the power supply voltage termination, an operation of the active termination circuit does not consume a current and it is not necessary to turn off the active termination circuit even though it is necessary to turn off the active termination operation.
Thus it is more effective to use a disable state of the operation signal of the active termination for adjusting a resistance value of the active termination circuit than turning off the active termination operation, in the semiconductor device with the power supply voltage termination. In fact, setting values of the termination setting codes of the MRS is only way to effectively turn off the active termination operation in the semiconductor device with the power supply voltage termination, regardless of the disable state of the operation signal of the active termination.
FIG. 1 is a table illustrating a comparison between active termination operations between a semiconductor device with an active termination circuit, and a semiconductor device with the power supply voltage termination as well as the active termination circuit.
For reference, an example of the semiconductor device with the active termination circuit is a double data rate three (DDR3) synchronous dynamic random access memory (SDRAM), and an example of the semiconductor with the power supply voltage termination as well as the active termination circuit is a DDR4 SDRAM. FIG. 1 compares specifications between the DDR3 SDRAM and the DDR4 SDRAM.
Referring to FIG. 1, in case of the DDR3 SDRAM, when an operation signal ODT of an active termination is disabled to logic LOW, an active termination operation is turned off, but when the operation signal ODT of the active termination is enabled to logic HIGH, termination resistance values are adjusted by termination setting codes A10, A9, A6 and A2 of MRS. When the values of the termination setting codes A10, A9, A6 and A2 of MRS are set to ‘0’, the active termination operation is turned off.
FIG. 1 shows two different MRS settings for ODT well-known in the field of the present invention: RTT_NOM (nominal on-die termination) mode and RTT_WR (dynamic on-die termination) mode, where the value of the termination resistance code can be set to turn off the active termination operation.
In case of the DDR4 SDRAM, when an operation signal ODT of an active termination is enabled to logic HIGH, the active termination operation is turned off due to the values of the termination setting codes A10, A9, A6 and A2 of MRS, which are set to ‘0’. When the operation signal ODT of the active termination is disabled to logic LOW, however, another well-known ODT operation mode RTT_PARK is performed without turn-off of the active termination operation. In the RTT_PARK mode, the active termination operation is turned off due to the values of the termination setting codes A8, A10, A9, A6 and A2 of MRS set to ‘0’.
As described above, in case of a conventional semiconductor device using the power supply voltage termination, in order to turn off the active termination operation, the values of the termination setting codes of the MRS should be set regardless of disablement of the operation signal ODT of the active termination.
The fact that setting of the MRS should be involved regardless of disablement of the operation signal to turn off the active termination operation in the semiconductor device with the power supply voltage termination raises a concern in a case that a plurality of semiconductor devices with the power supply voltage termination are arranged with a multiple die package.
FIG. 2A is a block diagram illustrating a conventional integrated circuit of the multiple die package structure including a plurality of semiconductor devices having the active termination circuit. FIG. 2B is a block diagram illustrating a conventional integrated circuit of the multiple die package structure including a plurality of semiconductor devices with the power supply voltage termination as well as the active termination circuit.
FIGS. 2A and 2B illustrate exemplary semiconductor devices that are the DDR3 SDRAM and the DDR4 SDRAM, respectively.
Referring to FIG. 2A, the plurality of semiconductor devices DRAM0 and DRAM1, which are DDR3 SDRAMs, share signal transmission lines DQS, DQSb and DQ0˜7. Active termination circuits AT0 and AT1 are included in each of the plurality of semiconductor devices DRAM0 and DRAM1. Each of the plurality of semiconductor devices DRAM0 and DRAM1 has a pad ODT for receiving an active termination operation signal ODT0 or VSS.
In the multiple die package structure of DDR3 SDRAMs, the plurality of semiconductor devices DRAM0 and DRAM1 share the signal transmission lines DQS, DQSb and DQ0-7, and thus it is not necessary to operate all of the active termination circuits AT0 and AT1 included in each of the plurality of semiconductor devices DRAM0 and DRAM1. Since the active termination operation is performed for an impedance matching with an external device, one of the plurality of semiconductor devices DRAM0 and DRAM1 is sufficient to perform the active termination operation and the rest of the plurality of semiconductor devices DRAM0 and DRAM1 needs not perform the active termination operation.
Thus, in case of a multiple die package structure of DDR3 SDRAMs, according to the active termination operation signal ODT0 that is enabled, a first semiconductor device DRAM0 of the plurality of semiconductor devices DRAM0 and DRAM1 shown in FIG. 2A performs the active termination operation. Whereas, according to the active termination operation signal VSS that is disabled, a second semiconductor device DRAM1 of the plurality of semiconductor devices DRAM0 and DRAM1 does not perform the active termination operation.
That is, in case of an integrated circuit of a multiple die package structure including a plurality of semiconductor devices having an active termination circuit, such as DDR3 SDRAMs, it is possible to simply turn off the active termination operation by adjusting an enable state or disable state of the active termination operation signal (ODT0 or VSS) that is input to each of the plurality of the semiconductor devices DRAM0 and DRAM1.
Referring to FIG. 2B, the plurality of semiconductor devices DRAM0 and DRAM1, which are DDR4 SDRAMs, share signal transmission lines DQS, DQSb and DQ0˜7. Active termination circuits AT0 and AT1 are included in each of the plurality of semiconductor devices DRAM0 and DRAM1. Each of the plurality of semiconductor devices DRAM0 and DRAM1 has a pad for receiving an active termination operation signal ODT.
In the multiple die package structure of DDR4 SDRAMs, the plurality of semiconductor devices DRAM0 and DRAM1 share the signal transmission lines DQS, DQSb and DQ0˜7, and thus it is not necessary to operate all of the active termination circuits AT0 and AT1 included in each of the plurality of semiconductor devices DRAM0 and DRAM1. Since the active termination operation is performed for an impedance matching with an external device, one of the plurality of semiconductor devices DRAM0 and DRAM1 is sufficient to perform the active termination operation and the rest of the plurality of semiconductor devices DRAM0 and DRAM1 needs not perform the active termination operation.
However, in case of the multiple die package structure having the plurality of semiconductor devices DRAM0 and DRAM1 shown in FIG. 28, setting of the MRS in each and every semiconductor device DRAM0 and DRAM1 should be involved regardless of the enable state or disable state of the active termination operation signal (ODT0 or VSS) to turn off the active termination operation in the semiconductor device with the power supply voltage termination, such as the DDR4 SDRAM, as described above in connection with FIG. 1. The enable state or disable state of the active termination operation signal (ODT0 or VSS) is not sufficient to control the active termination operation of each and every semiconductor device DRAM0 and DRAM1, such as DDR4 SDRAMs, of the multiple die package.
It is possible to turn off the active termination operation of one of semiconductor devices DRAM0 and DRAM1 shown in FIG. 28 by adjusting a setting value of the MRS of one of the semiconductor devices DRAM0 and DRAM1. However, it is not easy for a controller to set the MRS in each of semiconductor devices DRAM0 and DRAM1 to turn off the active termination operation of one of the semiconductor devices DRAM0 and DRAM1 included in the multiple die package structure. This may cause a deterioration of the performance of a semiconductor system.
That is, in case of an integrated circuit of a multiple die package structure including a plurality of semiconductor devices having an active termination circuit using a power supply voltage termination, since it is impossible to independently control turn-off of the active termination operation of each of the plurality of semiconductor devices by adjusting an enable state of the active termination operation signal that is input to each of the semiconductor devices, the MRS of each of the semiconductor devices has to be adjusted to turn off the active termination operation.